The utilization of SSRW designs is known to enhance device performance while suppressing a short-channel effect. Various device designs use a step-doping channel profile using Si:C. These designs use Si:C due to its capability to form an excellent p-type (boron (B) or indium (In)) diffusion barrier and to form a steep channel profile for n-channel MOSFETs (NFETs). Conventionally, SSRW profiles are achieved by ion implantation, which is limited by the diffusion of p-type dopants during subsequent thermal processes and is more difficult in technology nodes below 20 nanometers (nm). SSRW profiles have also been achieved by forming the Si:C diffusion barrier by blanket epitaxial growth before the formation of shallow trench isolation (STI) regions.
FIGS. 1A through 1C depict the conventional process for forming a p-type step-doped channel profile in silicon wafer 101. FIG. 1A illustrates an undoped silicon substrate 101 on which a Si:C layer 105 and a silicon cap layer 103 are grown epitaxially. Adverting to FIG. 1B, oxide STI regions 107 are formed to isolate later formed semiconductor devices from each other. As illustrated in FIG. 1C, a high energy p-type well implant 109 (e.g. of B, In, or boron fluoride (BF2)) is performed. (Alternatively, an N-well implantation, channel stop, or anti-punch through may be performed.) High energy and high dosage threshold voltage adjustment implants are required to achieve the desired dopant concentration 20 nm to 30 nm below the gate dielectric layer of the fabricated FET device. Due to limitations in the thickness of the photoresist material for such high energy and high dosage implantation, this method is difficult to apply for 20 nm and beyond fabrication technology. Further, this method cannot avoid dopant impurities in the channel surface region caused by the implanted ions migrating upwards during threshold adjust well implantation, thus causing threshold voltage variation and, therefore, degraded device performance.
If blanket epitaxial Si:C is grown after STI formation and chemical mechanical polishing (CMP) followed by an active silicon strip without precise control of step height between active regions and the field oxide, the active regions end up with a step height difference relative to the field oxide, causing process issues during later polysilicon gate electrode or replacement metal gate electrode formation. Polysilicon gate patterning is very sensitive to substrate topology and gate height varies significantly on the active regions and the field oxide at the gate CMP unless the step height is close to zero. Also, a blanket epitaxial growth may not be favorable to all FETs. For example, Si:C doping improves B diffusion for NFETs and may give some strain benefit (tensile) for NFETs. However, Si:C may not be favorable for PFETs (B source/drain profile may be changed). In most cases, the PFET threshold voltage increases with Si:C and may cause counter doping for threshold voltage centering, which could cause short channel control issues. Further, if carbon concentration needs to be high for NFETs, it may cause PFET ion degradation from tensile stress.
A need therefore exists for methodology enabling SSRW device formation which enables steep channel profile formation while using lower energy implants and the resulting device.